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AUTONOMOUS TIMING CLOSURE IN VLSI: A DEEP REINFORCEMENT LEARNING APPROACH FOR NEXT-GENERATION STA

2025-11-03

Abstract excerpt

The complexity of VLSI modern systems at advanced nodes makes timing closure a major bottleneck. Traditional iterative methods are slow, especially as design size and variability increase. [1] In this work, we introduce the Next-Generation Static Timing Analysis (NextGen STA) framework for Autonomous Timing Closure (ATC) based on Deep Reinforcement Learning (DRL) [7][8]. This paper presents the optimization proces...

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Literature Corpus work
912e1f37-2998-5aa1-ac37-d149b62b611b
DOI
10.22541/au.176216605.57590912/v1
Open publication

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AUTONOMOUS TIMING CLOSURE IN VLSI: A DEEP REINFORCEMENT LEARNING APPROACH FOR NEXT-GENERATION STADOI 10.22541/au.176216605.57590912/v1
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